Self-aligned barrier and capping layers for interconnects

Details for Australian Patent Application No. 2010310750 (hide)

Owner President and Fellows of Harvard College

Inventors Gordon, Roy Gerald; Bhandari, Harish; Au, Yeung; Lin, Youbo

Agent Davies Collison Cave

Pub. Number AU-A-2010310750

PCT Pub. Number WO2011/050073

Priority 61/385,868 23.09.10 US; 61/254,601 23.10.09 US

Filing date 20 October 2010

Wipo publication date 28 April 2011

International Classifications

H01L 21/285 (2006.01) Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L 21/768 (2006.01) Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L 23/532 (2006.01) Details of semiconductor or other solid state devices

Event Publications

7 June 2012 PCT application entered the National Phase

  PCT publication WO2011/050073 Priority application(s): WO2011/050073

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